1. Field of the Invention
The present invention relates to epitaxial growth of a crystalline material. The improved growth may occur within a confined area, such as within an opening or trench formed in an insulator.
2. Description of the Related Art
The formation of lattice-mismatched materials has many practical applications. Heteroepitaxial growth of group IV materials or compounds, and III-V, III-N and II-VI compounds on a crystalline substrate, such as silicon, has many applications such as photovoltaics, resonant tunneling diodes (RTD's), transistors (e.g., FET (which can be planar or 3D (i.e., finFET), HEMT, etc.), light-emitting diodes and laser diodes. As one example, heteroepitaxy of germanium on silicon is considered a promising path for high performance p-channel metal-oxide-semiconductor (MOS) field-effect transistors (FET) and for integrating optoelectronic devices with silicon complementary MOS (CMOS) technology. Heteroepitaxially growing Ge on Si also is a path for providing a substitute for Ge wafers for many other applications such as photovoltaics, light-emitting diodes, and laser diodes provided that a sufficiently high-quality Ge surface can be obtained cost-effectively. Heteroepitaxy growth of other materials (e.g., of group III-V, III-N, and II-VI compounds and other group IV materials or compounds) also is beneficial for these and other applications.
However, the dislocation density of the epitaxially grown material can be unacceptably high for many applications. For example, the dislocation density of germanium directly grown on silicon can be as high as 108-109 cm−2 due to the 4.2% lattice mismatch between the two materials—unacceptable for most device applications. Various approaches to reducing the defect density have been pursued, including compositional grading, and post-epi high-temperature annealing. However, these approaches may not be optimal for integration with silicon-based CMOS technology due to requirements for thick epi-layers and/or high thermal budgets, or due to incompatibility with selective growth at a density suitable for CMOS integration.
Aspect Ratio Trapping (ART) is a defect reduction technique which mitigates these problems. As used herein, “ART” or “aspect ratio trapping” refers generally to the technique(s) of causing defects to terminate at non-crystalline, e.g., dielectric sidewalls, where the sidewalls are sufficiently high relative to the size of the growth area so as to trap most, if not all, of the defects. ART utilizes high aspect ratio openings, such as trenches or holes, to trap dislocations, preventing them from reaching the epitaxial film surface, and greatly reduces the surface dislocation density within the ART opening. FIGS. 7A and 7B respectively show a cross section and perspective view of an epitaxially grown crystalline material 140 using ART. As illustrated, a crystalline material 140 is epitaxially grown on substrate 100 (here, on the (001) surface of a silicon substrate). By confining the crystalline growth within an opening (e.g., trench) with a sufficiently high aspect ratio (e.g, 1 or greater), defects 150 formed while epitaxially growing the crystalline material 140 travel to and end at the insulator sidewalls 130. Thus, the crystalline material 140 continues to grow without the continued growth of the defects 150, thereby producing crystal with reduced defects. This technique has been shown to be effective for growing low defectivity materials such as Ge, InP and GaAs selectively on Si in trenches as wide as 400 nm and of arbitrary length—an area large enough for devices such as a FET, for example.
Selective growth behavior on SiO2-patterned Si substrate is known to differ significantly from the growth on blanket substrates, due to the so-called “loading effect”. Thus, even when using the same process (temperature, pressure, time, precursor gas, etc.) are used to epitaxially grow material across a large area of a substrate (blanket epixatial growth) and on a substrate within an area confined by an insulator (e.g., on Si within an opening or trench in SiO2), different results may be obtained. Growth behavior depends not only on the total area ratio of Si-to-SiO2 over the wafer but also on the size of the openings of individual Si windows. It has been reported that the loading effect is reduced through a reduction of the growth pressure or through an addition of HCl to the growth ambient. Other studies have focused on the pattern dependence of the growth rate and germanium content of selective SiGe. However, there are few studies on selective Ge, especially on the initial growth stage of Ge which determines the surface morphology of the layer.
When manufacturing a device which includes an active portion of the crystal material within an opening of surrounding dielectric, it is often desirable to obtain a smooth crystal surface within the opening. For example, a high surface roughness of the surface of a lower layer (e.g., an n-doped crystalline layer) would create higher variances in an interface between this lower layer and an upper layer (e.g., a p-doped crystalline layer) formed on this lower layer from one location to the next. These interface variances affect the functionality of the interface from one device to another device on the same substrate (e.g., differences in diode devices formed by p-n junctions differ from variances of the junctions, or interfaces, of the p and n crystalline materials). Thus, the same devices produced on the same substrate (e.g., same sized diodes, transistors, LEDs, LD's, etc. on the same silicon wafer) may undesirably vary in their operational characteristics. This may result in requiring higher operating tolerances and possibly device failure.
For the growth of smooth Ge layers on a blanket substrate, two-step growth, which comprises a thin low temperature buffer (330-450° C.) followed by a thick high temperature layer (600-850° C.) has been utilized. However, none of these processes were shown to be able to create smooth surfaces of Ge in a confined location, such as an opening or trench in an insulator. As noted above, the selective growth (e.g., in an opening or trench) is known to differ from growth on blanket substrates. Further, growth at the lower temperatures was performed by molecular beam epitaxy, which is currently undesirable for commercial applications.
Chemical mechanical polishing (CMP) of the selectively grown crystalline material may not be an option to smooth the surface of the crystalline material if it is not desired to grind the surrounding dielectric layer to the same height. Further, known processes which obtain acceptable surface roughness for blanket expitaxial grown materials have been found to obtain higher surface roughness for selective epitaxial grown materials.
Thus, there is a need to reduce the surface roughness of materials grown in a confined area or selectively grown. In particular, there is a need to reduce the surface roughness of crystalline materials grown in an ART opening.